RFID Tag IC Silicon Directory & Benchmark Hub
The definitive engineering matrix of passive RAIN UHF, HF NFC, and Dual-Frequency RFID silicon chips.
Compare verified RF sensitivities (-25.5 dBm record),
complex input impedance models, GS1 EPC Gen2v2 memory allocations, and auto-tuning varactor engines across
Impinj, NXP Semiconductors, Alien Technology, and EM Microelectronic.
Manufacturer Clusters
Explore Dedicated Semiconductor Foundries
Deep architectural teardowns, wafer bond pad layouts, and register maps for each global RFID IC foundry.
Impinj Silicon Cluster
M800 (-25.5 dBm world-record), M700 (M730/M750), and Monza R6/R6-P. AutoTune v3 adaptive front-ends and Protected Mode.
NXP Semiconductors Cluster
UCODE 9 (-22 dBm write & 32 tags/sec parallel encoding), UCODE 9xm (880b NVRAM), NTAG 424 DNA (AES-128 SUN), and ICODE SLIX2.
Alien Technology Cluster
Higgs-9, Higgs-10, Higgs-EC, and Higgs-3. Sentinel™ hardware ECC memory architecture with 200,000 write cycle endurance.
EM Microelectronic & Sensors
EM4423/EM4425 dual-frequency RAIN+NFC, EM4325 BAP (-31 dBm / 50m range), and Axzon Magnus-S3 battery-free moisture/temp sensing.
Faceted Engineering Filter
Silicon IC Benchmark Comparison Matrix
Search, sort, and filter verified silicon specifications across read sensitivity, write speed, and TID schemas.
Interactive RFID Silicon IC Benchmark Matrix
Filter and cross-reference 18+ verified silicon endpoint ICs by read sensitivity, memory partitioning, TID prefixes, and auto-tuning hardware engines.
| Chip Model | Foundry | Read Sens | Write Sens | Δ Write | EPC | User | TID Prefix | Tuning Engine | Spoke Hub |
|---|---|---|---|---|---|---|---|---|---|
| EM Microelectronic EM4325 | EM Microelectronic | -31 dBm | -18 dBm | +13 dB | 496 b | 4096 b | E28016... | Static | Deep Dive → |
| Impinj M850 | Impinj | -25.5 dBm | -17.5 dBm | +8 dB | 96 b | 32 b | E28011B0 | AutoTune™ v3 | Deep Dive → |
| Impinj M830 | Impinj | -25.5 dBm | -17.5 dBm | +8 dB | 128 b | 0 b | E28011B1 | AutoTune™ v3 | Deep Dive → |
| Impinj M750 | Impinj | -24 dBm | -21 dBm | +3 dB | 96 b | 32 b | E2801190 | AutoTune™ v2 | Deep Dive → |
| Impinj M730 | Impinj | -24 dBm | -21 dBm | +3 dB | 128 b | 0 b | E2801191 | AutoTune™ v2 | Deep Dive → |
| NXP UCODE 9 | NXP Semiconductors | -24 dBm | -22 dBm | +2 dB | 96 b | 0 b | E28068A0 | Self-Adjust | Deep Dive → |
| NXP UCODE 9xm | NXP Semiconductors | -24 dBm | -22 dBm | +2 dB | 496 b | 752 b | E28068A... | Self-Adjust | Deep Dive → |
| Alien Higgs-10 | Alien Technology | -23.5 dBm | -19 dBm | +4.5 dB | 128 b | 32 b | E200... | Sentinel™ | Deep Dive → |
| NXP UCODE 8 | NXP Semiconductors | -23 dBm | -18 dBm | +5 dB | 128 b | 0 b | E2806894 | Self-Adjust | Deep Dive → |
| Alien Higgs-9 | Alien Technology | -22.5 dBm | -19 dBm | +3.5 dB | 496 b | 688 b | E2003821 | Sentinel™ | Deep Dive → |
| Alien Higgs-EC | Alien Technology | -22.5 dBm | -19 dBm | +3.5 dB | 128 b | 128 b | E2003811 | Sentinel™ | Deep Dive → |
| Impinj Monza R6-P | Impinj | -22.1 dBm | -17.3 dBm | +4.8 dB | 128 b | 64 b | E2801170 | AutoTune™ | Deep Dive → |
| Impinj Monza R6 | Impinj | -22.1 dBm | -18.8 dBm | +3.3 dB | 96 b | 0 b | E2801160 | AutoTune™ | Deep Dive → |
| EM Microelectronic EM4425 (em|echo-V) | EM Microelectronic | -20 dBm | -14.5 dBm | +5.5 dB | 448 b | 2048 b | E28016... | Dual-Port | Deep Dive → |
| Alien Higgs-3 | Alien Technology | -18 dBm | -13.5 dBm | +4.5 dB | 480 b | 512 b | E2003412 | Static | Deep Dive → |
| EM Microelectronic EM4423 (em|echo) | EM Microelectronic | -18 dBm | -13 dBm | +5 dB | 256 b | 1024 b | E28016... | Dual-Port | Deep Dive → |
| Axzon Magnus-S3 | Axzon | -16.6 dBm | -12 dBm | +4.6 dB | 128 b | 128 b | E28035... | Chameleon™ | Deep Dive → |
| NXP NTAG 424 DNA | NXP Semiconductors | NFC HF | NFC HF | - | 0 b | 3328 b | 04... | Static | Deep Dive → |
| NXP ICODE SLIX2 | NXP Semiconductors | NFC HF | NFC HF | - | 0 b | 2528 b | E004... | Static | Deep Dive → |
Electromagnetic Principles
The Physics of RF Silicon Sensitivity & Power Transfer
How logarithmic sensitivity gains and complex conjugate impedance matching govern real-world activation range.
1. The Friis Transmission Equation & The +3 dB Sensitivity Law
In passive backscatter RFID, the tag silicon contains no internal battery. It relies strictly on harvesting
electromagnetic energy radiated by the interrogator antenna. The maximum theoretical free-space activation distance
r_max is governed by the modified Friis transmission formula:
Because read distance is inversely proportional to the square root of the required chip sensitivity power
(r ∝ 1 / √P_sens), every +3 dB improvement in sensitivity
cuts the required activation power in half (50%) and
increases line-of-sight read range by:
Moving from a legacy chip at -18.0 dBm (e.g. Higgs-3) to a modern chip at
-24.0 dBm (e.g. UCODE 9 or M730) represents a
+6.0 dB sensitivity leap, which cuts activation power by 75% and
exactly doubles (+100%) the theoretical read range using identical antenna geometry.
2. Complex Impedance & The Power Transmission Coefficient (τ)
A silicon die exhibits a highly capacitive input impedance:
Z_chip = R_chip - j X_chip (typically
23 - j224 Ω at 915 MHz with internal die capacitance
C_p ≈ 1.04 to 1.20 pF).
To maximize power transfer, the tag antenna must present the complex conjugate:
Z_ant = R_chip + j X_chip.
When a tag encounters moist cardboard, beverage bottles, or metal shelving, the dielectric constant pulls the antenna resonance downward, causing severe impedance mismatch. Foundries resolve this using dynamic on-chip auto-tuning:
- Impinj AutoTune™: An integrated 5-step switched-capacitor varactor array adjusts internal capacitance by ±100 fF at power-up to conjugate-match antenna detuning.
- NXP Self-Adjust: Dynamically selects internal capacitance steps based on detected RF field impedance, recovering up to 6 dB of lost link budget.
Interactive Simulation Engine
Friis Free-Space Read Range Calculator
Model line-of-sight activation distances dynamically across chip sensitivities, reader power, and antenna gains.
Friis Free-Space Read Range & Sensitivity Simulator
Calculate theoretical line-of-sight activation distance based on electromagnetic backscatter power transmission:r = (λ / 4π) × √((P_EIRP × G_tag × τ) / P_sens)
Ideal anechoic chamber line-of-sight based on Friis equation.
Accounts for 50% multipath ground reflection, polarization loss & packaging material absorption.
Memory Architecture Tool
GS1 EPC Memory Allocator & Silicon TID Decoder
Size your EPC and User Memory requirements to identify matching silicon, or decode live 8-character TID headers.
GS1 EPC Memory Allocator & Silicon TID Decoder
Select required bit capacities to find matched silicon, or paste a live 8-character TID header to identify the chip foundry and hardware capabilities.
Step 1: Choose Application Memory Requirements
Standard GS1 SGTIN-96 retail apparel format (24 hex characters).
Zero user memory lowers gate count, maximizing read sensitivity and encoding speed.
Step 2: Live Silicon TID Header Decoder
Paste the first 8 to 12 hex characters read from Bank 10 (TID) to identify the chip model and feature set:
Laboratory & Converting Video
Silicon Die Optical Inspection & Flip-Chip Placement
High-speed optical inspection and micro-precision placement of silicon dies onto copper flip-tag antenna feeds.
High-Speed Optical Flip-Tag Silicon Die Inspection
Demonstration of automated optical inspection and high-speed pick-and-place bonding of passive UHF RFID silicon tag dies onto etched copper antenna substrates at 600+ tags/minute.
Frequently Asked Questions
RFID Silicon Engineering & Selection FAQs
Technical answers to common RF design, converting, and chip procurement queries.
What is an RFID Tag IC (Silicon Integrated Circuit)?
An RFID Tag Integrated Circuit (IC) is a microscopic semiconductor die (typically less than 0.5 mm × 0.5 mm fabricated on 40nm or 55nm CMOS nodes) that harvests RF energy from an interrogator electromagnetic field. It contains an analog RF rectifier, an impedance matching front-end, digital finite state machine logic, and non-volatile EEPROM memory partitioned into four GS1 EPC Gen2 banks (Reserved, EPC, TID, and User Memory).
Why is a 3 dB improvement in chip sensitivity so critical?
Under the Friis transmission equation, the maximum theoretical free-space activation range scales inversely with the square root of the required chip activation power (r ~ 1 / sqrt(P_sens)). A 3 dB improvement cuts the required RF power in half (50%), resulting in a theoretical range increase of sqrt(2) - 1 ≈ +41.4%. A 6 dB sensitivity leap (such as moving from -18 dBm to -24 dBm) exactly doubles (+100%) theoretical read range using identical antenna geometry.
What is the difference between Read Sensitivity and Write Sensitivity?
Read Sensitivity (e.g. -24.0 dBm for UCODE 9 or -25.5 dBm for Impinj M850) is the minimum RF power required to wake up the analog charge pump and backscatter the EPC. Write Sensitivity (e.g. -22.0 dBm for UCODE 9 vs -17.5 dBm for M850) is the much higher power required to write data to floating-gate EEPROM cells. Chips with a low write delta (such as NXP UCODE 9 at +2.0 dB delta) can be encoded at near-full read distance on high-speed industrial printing lines.
How does Impinj AutoTune and NXP Self-Adjust prevent tag detuning?
When a tag is placed on high-dielectric substrates (cardboard moisture, liquid containers, human apparel), the dielectric constant shifts the antenna resonance downward, causing severe impedance mismatch. Impinj AutoTune and NXP Self-Adjust feature on-die switched capacitor varactor arrays that dynamically adjust the chip's internal capacitance (typically in steps of +/- 100 fF) at startup, recovering 4 dB to 6 dB of lost link budget and eliminating warehouse blind spots.
Why do modern retail chips like Monza R6, Impinj M730, and UCODE 9 have 0 bits of User Memory?
Eliminating User Memory and password logic drastically reduces transistor gate counts, allowing foundries to shrink the physical silicon die size to under 0.3 mm². This reduction in die capacitance and active power drain simultaneously lowers manufacturing costs and delivers industry-leading read sensitivity (-24.0 dBm to -25.5 dBm). Modern supply chain architectures store product attributes in cloud databases indexed by the unique EPC, rendering on-tag User Memory redundant for retail.
When is large User Memory (such as NXP UCODE 9xm or Alien Higgs-9) mandatory?
Large User Memory (128 to 752+ bits) is required in offline, decentralized, or safety-critical deployments—such as aviation maintenance (ATA Spec 2000), automotive manufacturing WIP, railway rolling stock tracking, and defense logistics (DoD MIL-STD-129). In these environments, tags must store maintenance logs, tare weights, part numbers, and calibration dates directly on the asset without requiring continuous ERP network connectivity.